This invention relates to the field of digital-to-analog converter circuitry. In particular, this invention is drawn to methods and apparatus for reducing glitches and extraneous noise in digital-to-analog converter circuitry.
Digital-to-analog converter (DAC) circuitry is used in numerous electronics application. A DAC requires a finite amount of time to sense input codes and convert the codes to an analog value (e.g., current or voltage) that the DAC then provides at its output. A finite amount of time is also required for the output of the DAC to stabilize or settle upon the analog value. These time elements establish an upper boundary on the performance bandwidth of the digital-to-analog conversion process.
A current steering DAC architecture is particularly desirable for speed advantages over other architectures. A current steering DAC generates a differential current output that is typically applied to a current-to-voltage converting amplifier to produce a differential voltage output. Current steering DACs, however, tend to have relatively poor dynamic performance.
Transient voltages will appear at the DAC output due to the periodic code updates applied to the DAC. Although the effect is dependent upon the specific DAC architecture, the transients frequently manifest as a xe2x80x9csmearingxe2x80x9d of the analog output. This smearing can introduce distortion in a baseband signal even after application of a reconstruction filter. More succinctly, input code transitions for current steering DACs frequently result in a xe2x80x9cglitchxe2x80x9d in the output signal.
Various attempts have been made to reduce or eliminate the glitch for current steering DACs. Generally, the attempts focus on reducing the height or the width of glitch.
For example, one current steering DAC architecture uses thermometer encoding for the DAC internal current sources. Although this approach ensures that the height of the glitch is less than the smallest DAC current step size, one disadvantage of such an architecture is that 2N current sources are required, where N is the number of bits of resolution.
Another approach is to use a row of latches to resynchronize the edges of the input binary codes at the DAC input such that the delays between different codes are minimized. This approach attempts to reduce the width of the glitch. Aside from noise and area impact, this approach does not fully eliminate the glitch due to the residual mismatch in latch gate delays and DAC switches.
In view of limitations of known systems and methods, methods and apparatus for controlling digital-to-analog conversion circuitry are disclosed.
One digital-to-analog conversion circuit includes first and second digital-to-analog converters (DACs). Switch circuitry couples a selected output of each DAC to an output node. The switch circuitry couples the selected output of only one of the first and second DACs to the output node at any given time. In one embodiment, the switch circuitry couples the differential output of a selected exclusive one of the first and second DACs to a pair of output nodes. In one embodiment, when the differential output of the selected DAC is coupled to the output node pair, the differential output of the non-selected DAC is coupled to a throwaway node.
One embodiment of a sampling apparatus includes a first and a second digital to analog converter (DAC). Each DAC has a first and a second output. The second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. The apparatus includes a first switch for coupling the common node to the first switch node and a second switch for coupling the common node to the second switch node.
The first switch couples the common node to the first switch node in response to a first switch signal. The second switch couples the common node to the second switch node in response to a second switch signal. In one embodiment, active regions of the first and second switch signals do not overlap to ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.
In one embodiment the first and second switch nodes are connected to input nodes of a differential amplifier. In an alternative embodiment, the sampling apparatus further comprises buffer circuitry wherein the first and second switch nodes are coupled to the input nodes of the differential amplifier through the buffer circuitry.
In various embodiments the DACs, switches, buffer circuitry, and differential amplifier may be fabricated on an integrated circuit die such that they share a common semiconductor substrate within an integrated circuit package. The integrated circuit package may further include a power amplifier for driving external analog circuitry such as a telephone subscriber line.